About

The operation of the digital systems like processors is based on microscopic cables (paths) that present great variability in terms of signal propagation delay and are distinguished into fast and slow paths. The variability between fast and slow paths can reach up to 80%. This affects the performance because each digital operation must wait the slowest path (critical path). The problem of delay variability will continue to exist and increase in the future according to Moore's law. The industry is tackling this problem by developing new shrinking technologies in semiconductor manufacturing. The goal is to achieve better specifications in terms of performance and power consumption as expressed by the metric performance per watt. A transition to a smaller manufacturing dimension achieves an improvement in performance/watt of 15-25%. However these technologies have huge development costs and in addition the transistor shrinking capabilities are expected to reach their limit by 2030.

Solution & Product

Trimsignal’s solution incorporates a chip in the existing processor that adjusts the processor’s speed by detecting in real time which of the slower paths are active. Thus a processor can operate at several frequencies above nominal achieving a speed improvement of 35-60%. At the same time this technology allows to reduce the power consumption by reducing the voltage supply. Although the voltage reduction increases the propagation delay in the slower paths the impact on the speed is absorbed by the achieved acceleration achieving an improvement in performance/watt of 18-30% which competitive to the improvement that the shrinking technologies provide and considering the zero design and manufacturing cost as the original design remains unchanged. An additional benefit is the ability of the versioning of the original design while the operating specifications can be modified emphasizing on the speedup or power consumption based on the targeted product by incorporating the appropriate hardware.

Innovation & Scalability

An innovative digital design method that increases performance in digital devices up to 20-65% or decreases power up to 15-40% in any IC design. To the best of our knowledge, it is the only non-manufacturing technique that improves performance-per-watt (P/W) without a migration to a new manufacturing technology or a stressing of the device’s operation margins that ensure reliability. Each new chip technology improves the performance-per-watt (P/W) in average 15-25%, doubling the fab, the R&D, the design, the EDA and the market costs. The proposed approach provides an improvement 15-40% P/W, adjusting the clock signal at runtime without any cost. Considering the chip-shrinking technological deadlock for the next decades the proposed solution seems even more attractive. The innovation is outlined in the following condition: “If the critical circuit paths that bound the performance of a digital device, retain stable or inactive (their propagation is interrupted), they will not represent an operating frequency constraint.” A hardware-based scheduler exploits this condition boosting the device frequency without triggering errors. The critical paths’ detection is implemented before the passing of the chip’s combinational logic while a glitch-free clock multiplexer imports a new operating frequency without losing in transitional clock cycles, respecting the setup and the hold times. The proposed solution can be applied to any digital device, regardless complexity or size.

Traction & achievements

The submission of the first patent began very early in 2016 as a provisional patent application at the US patent office In order to explore the potential of our technology we had the opportunity to speak with companies in Silicon Valley like Xilinx and after realizing the prospects of our technology we submitted the final applications along with the US patent office to the international patent organization WIPO two years later. After the successful completion of the PCT international process where we managed to secure almost all of the claims internationally we are in the national phases since 2019 in Europe Japan China and India It is noted that the time-consuming process of the US patent was completed in April 2020 The goal is to cover the full range of applications from design tools and digital systems development to the distribution of final products in the international market. In addition we are in contact with funds active in the IP market and we are exploring a potential collaboration with one of the largest intellectual property managers for high-tech companies.

Team & Why Us

Nikolaos Zompakis is the CEO and founder of Trimsignal. He is a digital design expert with more than fifteen years experience as a PhD research project assistant designing SoC and multi-core platforms for advanced mobile and high performance systems. His expertise is in clock architectures with particular knowledge in VLSI design. As Trimsignal’s CEO, Mr. Zompakis is responsible for R&D, product and business development, project management, and financial operations.

Funding Needs

TRIMSIGNALTM is seeking an investment of 300-500K euro. Company believes this investment is necessary to ensure there are sufficient funds available to meet expected financial obligations, the principle being patent prosecution expenses for a large global patent portfolio. Company is currently an LLC. A portion of funding will be used to create a new corporate entity, under which the LLC will likely become a wholly owned subsidiary.